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V320 8-Bit Registered Bus Transceiver
April 1998 Revised October 1998
V320 8-Bit Registered Bus Transceiver
General Description
The V320 is an 8-bit universal bus transceiver designed for high speed interfacing with the VME320 backplane. It has output characteristics optimized for driving large capacitive loads and features modified input levels (VIH/VIL) for increased noise immunity and reduced input skew. The V320 functionality consists of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or in both. The select controls can multiplex stored and real time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is active LOW. In the isolation mode (OE HIGH) A data may be stored in the B register and/or B data may be stored in the A register.
Features
s Independent registers for A and B buses s Multiplexed real-time and stored data s Guaranteed output skew s Guaranteed MOS (Multiple Output Switching) Specifications s Output switching specified for both 50 pF and 250 pF, and 500 pF loads s Guaranteed simultaneous switching noise level (VOLP/ VOLV) and dynamic threshold performance (VIHD/VILD) s Glitch free power up/down high impedance for live insertion s BiCMOS technology for high drive and low power dissipation s -40C to 85C commercial temperature and VCC specifications s Modified specifications across VCC and temperature (VCC = 5.0V 1%, T = 25C 20C) present more realistic system conditions s Available in TSSOP (MTC)
Ordering Code:
Order Number V320MTC Package Number MTC24 Package Description 24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names D OE CLKAB/SELAB CLKBA/SELBA A0-7 B0-7 Description Direction A-to-B (High) B-to A (Low) Output Enable (Active LOW) A-to-B Clock/Select B-to-A Clock/Select A Inputs/Outputs (TTL) B Inputs/Outputs (TTL)
(c) 1998 Fairchild Semiconductor Corporation
DS500149.prf
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V320
Functional Table
OE H H H L L L L L L L L D X X X H H H H L L L L SELAB SELBA CLKAB CLKBA X X X L L H H X X X X X X X X X X X L L H H H or L LH X X LH H or L LH X X X X H or L X LH X X X X X LH H or L LH Output Input Input Input Input A0-A7 B0-B7 Isolation CLK A Data into A CLK B Data into A Reg. A to B - Transparent CLK A Data into A Reg. Output A Reg. to B (Storage) CLK A Data into A Reg. and B output B to A - Transparent CLK B Data into B Reg. B Reg. to A (Storage) CLK B Data into B Reg.and A output Function
L = Low H = High LH = Low to High transition X = Don't Care
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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V320
Absolute Maximum Ratings(Note 1)
DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 2) DC Output Sink Current into A-port/B-port IOL DC Output Source Current from A-port/B-port IOH DC Input Diode Current (IIK) VI < 0 V ESD Rating typical Storage temperature (TSTG) Max IOL (Current Applied to a LOW Output) -30 mA to +5.0 mA > 2000V -65 C to +15C 2 X IOL Spec. -0.5V to +7.0V -0.5V to VCC +0.5V 64 mA -32 mA -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage VCC Operating VCC Minimum Input Edge Rate Data Input Enable Clock Operating Temperature (TA) 50 mV/ns 20 mV/ns 100 mV/ns -40C to +85C 4.5V to 5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics (4.5V < VCC 5.5V)
Over Recommended Operating Free-Air Temperature Range (Unless Otherwise Noted) VCC Symbol Parameter Min Typ (V) VIH B-Port/A-Port HIGH Level Input Voltage 4.5-5.5 4.95-5.05 VIL B-Port/A-Port LOW Level Input Voltage 4.5-5.5 4.95-5.05 VOH IOH VOL IOL IOS IOFF ICCH ICCI ICCZ B-Port/A-Port HIGH Level Output Voltage B-Port/A-Port High Level Output Current Drive B-Port/A-Port LOW Level Output Voltage B-Port/A-Port Low Level Output Current Drive (Sink) B-Port/A-Port Short Circuit Current A-Port and Control Pins Power-OFF Leakage Current 4.5 4.5 4.5 4.5 4.5 5.5 0.0 5.5 5.5 5.5 2.5 2.0 -32 0.55 64 -100 -275 100uA 250 30 50 mA V mA mA uA uA mA uA 2.0 1.8 (Note 3) 0.8 1.2 (Note 3) V -3 mA -32 mA VOH = 2.0V 64 mA VOL = 0.55V VOUT = 0.0V VOUT = 5.5V, All Others GND All Outputs HIGH All Outputs LOW All Outputs 3-STATE V Recognized LOW Signal Max Units V Conditions Recognized HIGH Signal
B-Port/A-Port Quiescent Power Supply Current B-Port/A-Port B-Port/A-Port B-Port/A-Port 3-STATE Power Supply Current
Note 3: Extended Characteristics (4.95 > VCC > 5.05, T = 25C 20C)
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V320
Capacitance and Dynamic Switching Characteristics
Over Recommended Operating Free-Air Temperature Range (Unless Otherwise Noted) Symbol Parameter Min Typ Max TA = 25C CIN CI/O VOLP VOLV VOHV VIHD VILD Input Capacitance (Control Pin) Output Capacitance (A and B ports) Quiet Output Dynamic Peak VOL Quiet Output Dynamic Valley VOL Quiet Output Dynamic Valley VOH High Level Threshold Movement Low Level Threshold Movement -1.2 2.5 2.2 0.5 5 11 0.8 pF pF V V V V V VCC = 5.0V, T= 25C CL = 50 pF VCC = 5.0V VI = VCC or 0 VCC = 5.0V VI = VCC or 0 VCC = 5.0V, T= 25C CL = 50 pF Units Conditions
Output Switching Noise (Ground Bounce)
Input Noise Immunity (Dynamic Threshold)
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature Symbol fCLOCK tWIDTH tSU tHOLD Max Clock Frequency Pulse Duration Setup Time Hold Time HIGH or LOW Bus to CLKAB/CLKBA Bus to CLKAB/CLKBA Min 200 (Note 4) 3.0 1.5 1.0 Typ Max Units MHz ns ns ns
Note 4: CL = 50 pF
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V320
AC Electrical Characteristics (-40C to 85C, VCC = 4.5V to 5.5V) 1 Output Switching
Symbol From (Input) Mode To (Output) Min Typ Max Units
Output Load: CL = 50 pF, RL= 500, 1 Output Switching tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 1.7 1.5 1.5 1.5 1.5 1.5 1.5 0.3 0.3 5.6 4.8 5.9 6.0 6.3 6.0 6.3 1.2 1.4 ns ns ns ns ns ns ns ns ns
Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V)
Output Load: CL = 250 pF, RL = 500, 1 Output Switching tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 2.0 2.0 2.0 (Note 5) 2.0 (Note 5) 2.0 1.7 0.8 7.5 7.0 7.5 (Note 5) 8.0 (Note 5) 8.3 3.9 3.1 ns ns ns ns ns ns ns ns ns
Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V)
Output Load: CL = 500 pF, RL = 500, Output Switching tPLHtPHL tPLHtPHL tPLHtPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 3.0 3.0 3.0 (Note 5) 3.0 (Note 5) 6.3 3.5 1.4 12.2 11.6 12.4 (Note 5) 12.6 (Note 5) 13.2 7.2 5.1 ns ns ns ns ns ns ns ns ns
Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V)
Note 5: 3-STATE delays are dominated by the RC Network (500 / 250 pF, or 500 / 500 pF) on the output and thus have been excluded from this datasheet.
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V320
AC Electrical Characteristics (-40C to 85C, VCC = 4.5V to 5.5V) 8 Output Switching
Symbol From (Input) Mode To (Output) Min Typ Max Units
Output Load: CL = 50 pF, RL = 500, 8 Outputs Switching tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tOSHL tOSHL tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 1.5 1.5 1.5 1.5 1.5 1.5 1.5 6.6 6.3 6.6 6.6 6.6 6.6 7.6 1.3 1.1 0.5 0.4 1.5 1.9 ns ns ns ns ns ns ns ns ns ns ns
Output to Output Skew (Note 6) Output to Output Skew (Note 6) Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V)
Output Load: CL = 250 pF, RL = 500, 8 Outputs Switching tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tOSHL tOSLH tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 2.5 2.5 2.5 (Note 8) 2.5 (Note 8) 2.5 11.2 9.5 11.2 (Note 8) 11.5 (Note 8) 13.5 2.5 2.0 2.0 1.4 5.5 4.4 ns ns ns ns ns ns ns ns ns ns ns
Output to Output Skew (Note 8) Output to Output Skew (Note 8) Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V)
Output Load: CL = 500 pF, RL = 500, 8 Outputs Switching tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tOSHL tOSLH tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 3.5 3.5 3.5 (Note 8) 3.5 (Note 8) 3.5 17.0 15.9 17.0 (Note 8) 18.5 (Note 8) 22.3 3.9 3.1 4.4 2.5 7.8 6.6 ns ns ns ns ns ns ns ns ns ns ns
Output to Output Skew (Note 6) Output to Output Skew (Note 6) Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V)
Note 6: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specification applies to outputs switching in the same direction also. Note 7: Device to Device Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs from any two devices. Note 8: 3-STATE delays are dominated by the RC Network (500 / 250 pF, or 500 / 500 pF) on the output and thus have been excluded from this datasheet.
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V320
Extended AC Electrical Characteristics (5C to 45C, VCC = 4.95V to 5.05V), 1 Output Switching
Symbol From (Input) Mode To (Output) Min Typ Max Units
Output Load: CL = 50 pF, RL = 500, 1 Output Switching tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tPV tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 1.5 1.5 2.0 1.5 2.2 1.5 2.2 5.2 4.3 4.8 6.0 5.0 6.0 5.2 2.0 3.0 0.4 1.2 1.2 ns ns ns ns ns ns ns ns ns ns
Device to Device Skew (Note 10) Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V)
Output Load: CL = 250 pF, RL = 500, 1 Output Switching tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tPV tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 2.5 2.5 3.0 (Note 9) 3.2 (Note 9) 3.2 7.4 6.7 7.2 (Note 9) 7.2 (Note 9) 8.1 2.5 2.1 1.0 3.5 2.5 ns ns ns ns ns ns ns ns ns ns
Device to Device Skew (Note 10) Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V)
Output Load: CL = 500 pF, RL = 500, 1 Output Switching tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tPV tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Device to Device Skew Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V) 3.8 1.7 Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 3.5 3.5 4.0 (Note 9) 4.2 (Note 9) 4.2 10.6 10.0 10.6 (Note 9) 10.5 (Note 9) 11.3 5.0 6.4 3.8 ns ns ns ns ns ns ns ns ns ns
Note 9: 3-STATE delays are dominated by the RC Network (500 / 250 pF, or 500 / 500 pF) on the output and thus have been excluded from this datasheet. Note 10: Device to Device Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs from any two devices.
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V320
Extended AC Electrical Characteristics (5C to 45C, VCC = 4.95V to 5.05V), 8 Outputs Switching
Symbol From (Input) Mode To (Output) Min Typ Max Units
Output Load: CL = 50 pF, RL = 500, 8 Outputs Switching tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tOSHL tOSLH tPV tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 2.5 2.5 2.5 1.5 2.5 1.5 2.5 6.2 5.4 5.7 6.0 5.7 6.0 7.2 1.1 0.9 2.5 0.5 0.6 1.3 1.4 ns ns ns ns ns ns ns ns ns ns ns ns
Output to Output Skew (Note 12) Output to Output Skew (Note 12) Device to Device Skew (Note 13) Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V)
Output Load: CL = 250 pF, RL = 500, 8 Outputs Switching tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tOSHL tOSLH tPV tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 3.5 3.5 3.5 (Note 11) 3.5 (Note 11) 3.5 10.5 10.5 10.5 (Note 11) 10.5 (Note 11) 14.8 2.3 1.9 4.0 2.7 1.8 4.7 3.7 ns ns ns ns ns ns ns ns ns ns ns ns
Output to Output Skew (Note 12) Output to Output Skew (Note 12) Device to Device Skew(Note 13) Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V)
Output Load: CL = 500 pF, RL = 500, 8 Outputs Switching tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLZ, tPHZ tPZH, tPZL tPLZ, tPHZ tPZH, tPZL tOSHL tOSLH tPV tRISE tFALL CLKAB/CLKBA Bus A or B SELAB/SELBA OE OE Direction (D) Direction (D) Register Transparent Select Bus Output Disable Output Enable Dir. Disable Dir. Enable Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B Bus A or B 5.0 5.0 5.0 (Note 11) 5.0 (Note 11) 5.0 15.3 13.6 15.3 (Note 11) 15.1 (Note 11) 19.4 3.5 2.9 5.0 4.6 2.9 7.0 4.9 ns ns ns ns ns ns ns ns ns ns ns ns
Output to Output Skew (Note 12) Output to Output Skew (Note 12) Device to Device Skew Transition Time, Outputs (1V to 2V) Transition Time, Outputs (1V to 2V)
Note 11: 3-STATE delays are dominated by the RC Network (500 / 250 pF, or 500 / 500 pF) on the output and thus have been excluded from this datasheet. Note 12: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specification applies to outputs switching in the same direction also. Note 13: Device to Device Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs from any two devices.
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V320
AC Loading and Waveforms
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 4. Propagation Delay, Pulse Width Waveforms
FIGURE 2. Test Input Signal Levels Input Pulse Requirements Test Input Signal Requirements
Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns
FIGURE 5. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 3. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 6. Setup Time, Hold Time and Recovery Time Waveforms
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V320 8-Bit Registered Bus Transceiver
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Thin Shrink Small Outline Package, JEDEC MO-153, 4.4mm Wide Package Number MTC24
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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